1. Field of the Invention
This invention relates to a sense amplifier latching circuit and more particularly to a sense amplifier latching circuit having self-isolation and fabricated from both depletion and enhancement mode field effect transistors.
2. Description of the Prior Art
The above-mentioned Sonoda patent exemplifies the prior art in memory arrays in which the present sense amplifier latch would be used. The above-mentioned Palfi patent is another example of a memory cell which could have its output sensed by the sense amplifier latching circuit of the present invention. The references cited in each of the foregoing two patents may also be referred to as being pertinent to the environment of the present invention. The prior art abounds with sense amplifiers, latches, and sense amplifier latch combinations for sensing the output of such memory cells. Generally, such memory cells have a pair of bit lines associated therewith for writing information into, and reading information out of such memory cells. Sense amplifiers are also connected to each of the pair of bit lines and typically detect a difference in either voltage or current (or both) on each of the pair of bit lines to determine whether a binary "0" or "1" was stored.
One type of such a sense amplifier is known to utilize a pair of cross-coupled field effect transistors and a third transistor used to establish a race condition between the cross coupled transistors after a difference in signal level has been impressed across the pair of bit lines. Once such sense amplifier is shown in U.S. Pat. No. 3,795,898, in which the cross coupled pair are transistors Q106 while the third transistor is identified as Q100, all in FIG. 1 of the Patent. A significant disadvantage of this last mentioned patented sense amplifier is that it is not isolated from the bit lines. Thus, after the race condition has been established and the sense amplifier latch is fully set, the bit lines have a full logic voltage difference impressed across them. Prior to the next memory cycle, it is necessary to restore the pair of bit lines to the same (binary up-level) potential, consuming time and power. One known technique for isolating the bit lines from such a cross-coupled sense amplifier latch is shown in U.S. Pat. No. 3,600,609. This last mentioned Patent, however, requires that the isolation transistors 14 and 16 be separately gated and further, cause the bit lines to be connected to the sense amplifier latch during the establishment of the race condition. Thus the bit lines will still be brought to a full logic level difference in potential.
As further background to the present invention, enhancement and depletion type field effect transistors have been used in previous circuit configurations as described in great detail in the cross referenced application by Freeman et al., the inventive entity of the present application. As was there particularly pointed out, the combination of the enhancement mode field effect transistors and the depletion mode field effect transistors as inverters was found to be superior to an inverter employing enhancement mode field effect transistors only, because the efficiency is higher and the transient response faster. The current through a depletion mode field effect transistor remains substantially constant as the output voltage transitions go toward the drain supply voltage, thus providing significantly greater switching speeds. The depletion field effect transistor can also be made significantly smaller than an enhancement mode field effect transistor used for the same purpose, particularly where switching speed is not required. Also, a depletion mode field effect transistor does not have the threshold voltage drop associated with enhancement mode field effect transistors so that when used as load devices, the output node between the signal transistor and the load device can be brought to a full binary up level. The aformentioned advantageous combination of depletion and enhancement mode field effect transistors in a self-isolated cross-coupled sense amplifier latched circuit were not known prior to the present invention.